Neel Patel

I am a Ph.D. Student at Cornell Computer Systems Lab and an SRC Jump 2.0 research scholar. My advisor is Prof. Mohammad Alian.

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My current research has focused on runtime development and data movement optimizations for accelerated systems.

A hardware architecture and runtime system that evades the danger of end-to-end slowdowns when using hardware acceleration by leveraging a low-overhead interface between general-purpose cores and on-chip accelerators, fine-grained context switching, accelerator-initiated preemption, and seamless data motion between general-purpose cores and accelerators.

A runtime for accelerated CMPs, designed to scale to many-core, many-accelerator CPUs, which achieves up to 3.2× higher throughput-under-SLO and never introduces slowdowns from using on-chip accelerators.

A near-memory system architecture (prototyped on Samsumg's AxDIMM), which accelerates datacenter upper layer network protocols--i.e. (de/en)cryption and (de)compression. In comparison to a server executing (de/en)cryption and (de)compression on the CPU, SmartDIMM achieves 21.0% to 10.28× higher requests per second and 36.3% to 88.9% lower memory bandwidth utilization.

We develop a near-memory accelerated far memory tier, which expands memory capacity through application-transparent (de)compression. FPGA implementation, simulation, and analytical modeling shows 5-27% memory and cache utilization reduction for a far memory tiers with a 1TB capacity.

Intelligent Knowledge Store (IKS), a type-2 CXL device that implements a scale-out near-memory acceleration architecture with a novel cache-coherent interface between the host CPU and near-memory accelerators. IKS offers 13.4–27.9× faster exact nearest neighbor search over a 512GB vector database compared with executing the search on Intel Sapphire Rapids CPUs.

A detailed architectural analysis of the gem5 source code on different server platforms.

An intelligent direct I/O (IDIO) technology that extends DDIO to the MLC. Reduces data movement (up to 84% MLC and LLC writeback reduction), provides LLC isolation (up to 22% performance improvement), and improves tail latency (up to 38% reduction in 99 th latency) for receive-intensive network applications.

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